1. Field of the Invention
The present invention generally relates to integrated circuit structures and manufacturing methods and, more particularly, to structures having at least one chip and connection pins bonded to opposite sides of a substrate.
2. Description of the Prior Art
The demand for miniaturized electronic circuits of greater complexity has led to the development of device constructions in which one or more integrated circuit chips are bonded to a substrate which is used to provide a complex interconnection wiring pattern. Multiple chips are typically provided in such devices, particularly if the overall function of the device requires chips which must be fabricated by different technologies. Even though some hybrid devices have been made which successfully combine high performance circuit element (e.g. transistor) designs on a single chip, such as bipolar and CMOS (complementary metal-oxide-semiconductor) technologies, there are many circumstances where the necessary metallurgical techniques to form different circuit elements cannot be resolved on a single chip. Further, some issues of manufacturing yields of chips and practicalities of scale (e.g. chip size at a given integration density) and other chip design and fabrication considerations dictate the use of multiple chips in a single device or at least the use of a substrate to provide a connection pattern between connection pins, by which the device may be installed in a larger circuit, and connection pads on the chip or chips.
Particularly successful technologies for the fabrication of such substrates are so-called glass and multi-layer ceramic (MLC) structures. Both of these technologies are well-known in the art and need not be discussed in detail to provide an understanding of the present invention. The basic characteristic of such structures and others to which the present invention is applicable is that the substrates are fabricated from layers where each layer is predominantly insulative with conductive areas therein. The registration of the layers and connections therethrough (referred to as vias in MLC technology) can be used to develop highly complex interconnection topologies while pads on the top and bottom layers permit bonding to chips and connection pins, respectively.
Since these and similar technologies are relatively well-developed, the fabrication of such substrates is generally fairly economical. However, at the present state of the art, significant costs are involved in the bonding of chips and connection pins to the substrate. Specifically, the bonding of connection pins (hereinafter simply "pins") and chips have been done in two operations, each typically including a plurality of steps and generally using solder preforms of a fusible or reflowable material. As is well-recognized in the art, each step of manufacturing carries specific economic costs in terms of time, equipment, overhead, throughput and yield. Additionally, the use of solder preforms in two separate operations requires solder preform materials which reflow at different temperatures (e.g. at least one of the bonding steps must be done at a relatively elevated temperature and subsequent steps at relatively lower temperatures). Further, to ensure good connection during such solder reflow at a temperature only slightly above the melting point of the solder preforms, precious metals such as gold have been required for the connection pads on the top and bottom of the substrate. This requirement for gold in or on connection pads of the substrate is a very significant factor in the total cost of the complete device.
It should also be understood that at the present state of the art, it is considered economical to repair devices which are defective due to connection defects within the substrate or defective chips. The problems of the prior art with regard to manufacture of devices including chips and pins bonded to substrates apply equally to repair of such devices. For this reason, and the fact that most such repairs, in fact, are performed as an incident to the fabrication process, the terms manufacture and fabrication should be understood as generic to both initial fabrication and repair, regardless of whether such repairs are conducted after initial fabrication and electrical testing or even after the device has been placed in service.